CMOS Multichannel Single-Chip Receivers for Multi-Gigabit by Paul Muller, Yusuf Leblebici

By Paul Muller, Yusuf Leblebici

Whereas the throughput of microprocessor structures has a tendency to extend because of ongoing expertise scaling and the appearance of multi-core platforms, the off-chip I/O communique bandwidth emerges as one of many capability bottlenecks that restrict performance. on the way to alleviate the verbal exchange velocity constraints, optical facts verbal exchange interfaces circulate ever in the direction of the processor middle. it truly is generally anticipated that destiny iteration electronic structures will more and more depend upon chip-to-chip and board-to-board optical facts communications for larger bandwidth and higher noise immunity.This e-book makes a speciality of optical communications for brief and extremely brief distance functions and discusses the monolithic integration of optical receivers with processing components in commonplace CMOS applied sciences. CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical facts Communications offers the reader with the mandatory historical past wisdom to completely comprehend the trade-offs in short-distance conversation receiver layout and offers the most important concerns to be addressed within the improvement of such receivers in CMOS applied sciences. furthermore, novel layout techniques are awarded. A system-level layout method enables the impression research of other block necessities and system-wide layout optimization. Statistical versions are used for layout house exploration within the scope of jitter tolerance research of clock restoration circuits.CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical facts Communications is needed studying for practising engineers and researchers within the box of short-distance optical communications and optical CMOS receiver layout.

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5) would require a lot of “memory” to maintain the correct clock rate during that process and “memory” (interestingly like digital memory) requires considerable chip area. While scrambling increases somewhat the number of data transitions, more benefits can be gathered from 8b/10b data encoding. The name indicates that the encoder outputs 10 bits of data for each eight incoming bits, resulting in a data rate loss of 20%. 6% or 60%) equivalent to a reduced low-frequency spectral content, it also guarantees a DC-balanced output signal (no spectral energy at DC) and an absolute maximum run length (5 bits).

The amplifiers and the CDR. In order to be competitive, the die area occupied by an optical receiver shall be comparable or smaller than the one occupied by an equivalent electrical I/O interface, when scaled by the data rate, a metric one could call area-pergigabit per second. g. operating at 800 Mb/s. As a differential scheme, it occupies two bond pads with associated 32 System-Level Specifications electrostatic discharge (ESD) protection and the LVDS driver or receiver. In advanced technologies, the bond pad area can be as small as 50×50 um2 with a pitch of 60 µm (and as low as 40 µm in staggered configuration).

As clock recovery does not require the same gain-bandwidth product and is commonly built with logic gates, it is fabricated in standard CMOS. This technologybased breakup remains more or less valid for the limited amount of currently available multichannel receiver solutions [27, 2]. 1. Components of a single-channel fiber-optic receiver The rationale behind the goal of monolithic integration has already been discussed in the previous chapters. Following the introduction of the system-level specifications, this chapter describes a topdown methodology to obtain the block-level specifications from the system level constraints.

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