Advances in Electronics and Electron Physics, Vol. 86 by Peter W. Hawkes (ed.)

By Peter W. Hawkes (ed.)

This sequence covers a variety of subject matters, stretching from the particle optics of accelerators, mass spectrometers, electron and ion microscopes, and of person parts of those tools to theoretical and sensible features of contemporary electroinics. one other vast intterest is electronic photograph processing and development acceptance, together with the units hired and the tools constructed. Electron physics is interpreted very liberally and articles are frequently incorporated on fabrics of present curiosity in addition to at the units that hire them. the article of the sequence is to supply articles that can evaluation a brand new or quickly constructing box, or may possibly hide a long time of study, therefore delivering a small monograph on a selected topic. "Advances in Electronics and Electron Physics" quantity 86 good points articles at the following themes: GaAs semiconductor thoughts; picture processing; N-beam calculators; and electron optics.

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Extra resources for Advances in Electronics and Electron Physics, Vol. 86

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30 shows drain current in a 10 x 350pm ring-gate MESFET. At room temperature, the gate-to-drain leakage in the JFET is more than two orders of magnitude smaller than in the MESFET. Thus, one expects superior storage time performance from a JFET-based memory. , 1991a). (It is important in this procedure that the metal not be deposited in an electron-beam evaporator). 0 Gate Voltage (V) FIGURE30. Drain current vs. gate voltage for a 10 x 350 pm ring-gate MESFET. Note that at room temperature the gate-to-drain leakage in the MESFET is more than two orders of magnitude higher than in the JFET of Fig.

The drastic reduction in storage time is the result of increased gate leakage in the MESFET as compared to JFET. This effect will be discussed next. RECENT ADVANCES IN GaAs DYNAMIC MEMORIES L - P5 Cell Capacitance Signal 4 : 1 - Q c , 3-5 5 -0 ’ 37 r Bit Line Voltage 2 - -_ s” 1 psec Pulse - 1 - *-Write MESFET Gate (Word Line) Voltage 0 I I I I I I I I FIGURE 26. Writing waveforms for the MESFET DRAM cell of Fig. 25. The top trace is the cell capacitance, the middle trace is the bit line voltage, and the lower trace is the write pulse train applied to the word line.

Equation ( 5 ) can be used to calculate both these capacitances. The total capacitance of the pnp structure measured in steady state is then The total charge stored is given by (7) evaluated for the reverse-biased junction (junction 2): The steady-state capacitance-voltage relationship (V, swept away from 0 ) is illustrated for two values of NA2in Fig. 8. , NA2# NAI), the capacitance-voltage relationship will not be symmetrical about VA= 0. Figure 8 shows a decreasing capacitance when the voltage is swept away from 0 in either direction (assuming quasi-steady-state conditions), and a different, almost flat, capacitance if the voltage is swept rapidly back toward 0.

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